Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure

ABSTRACT

An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a second gate dielectric. The second gate dielectric includes an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.

This is a continuation of U.S. application Ser. No. 11/183,224, which was filed Jul. 14, 2005 and is now U.S. Pat. No. 7,202,535, issued Apr. 10, 2007.

TECHNICAL FIELD

The present invention relates to a manufacturing method for an integrated semiconductor structure and to a corresponding integrated semiconductor structure.

BACKGROUND

U.S. Pat. No. 5,843,812 describes a manufacturing process of a p-MOSFET having a polysilicon gate wherein a BF₂ ion implantation is performed into the polysilicon gate in order to achieve a more stable threshold voltage.

Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.

To improve the speed of the periphery devices, the device length as well as a gate oxide thickness have to be scaled down. Below a certain thickness of 2 nm, the gate leakage is very important and increases exponentially. High-k dielectrics are supposed to improve the gate oxide problem. However, the integration of the high-k dielectric together with a N⁺ polysilicon gate is very difficult due to the fermi-level pinning.

Also, gate polysilicon depletion is becoming a limiting factor for on-current of small gate-length transistors with a thin gate dielectric having a thickness of less than about 2 nm. The gate poly-depletion effect usually contributes to a 7-10×10⁻¹⁰ m (Å) increase of the overall effective oxide thickness of the gate dielectric for logic devices. The gate polysilicon depletion is even more severe for p-MOSFETs in DRAM support devices due to the higher boron deactivation during DRAM processing.

Metal gates which are free from poly-depletion effects have been anticipated for replacement of polysilicon gates. However, issues such as a process compatibility, device reliability and difficulties in integrating dual work-function metal gates for both p- and n-MOSFETs have hindered the introduction of metal gates. Though p-MOSFETs with an N⁺ polysilicon gate are also free from polysilicon depletion effect, the threshold voltage will be too high for any practical application due to the improper work-function of the N⁺ polysilicon.

SUMMARY OF THE INVENTION

The object of the present invention is to provide an improved manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure where the Fermi-level of the p-MOSFET may be properly adjusted.

The basic idea underlying the present invention is to enhance p-MOSFET performance by eliminating the gate polysilicon depletion while maintaining the appropriate threshold voltage. An N⁺ polysilicon gate is used as gate electrode since it is free from gate polysilicon depletion for p-MOSFETs. Moreover, a thin interfacial high-k dielectric layer, preferably an Al_(x)O_(y) layer, between the N⁺ polysilicon gate and the gate dielectric is introduced in the p-MOSFET, only. This interfacial high-k dielectric layer is chosen such that it has strong Fermi-level pinning effects on the N⁺ gate polysilicon. As a consequence, the effective work-function for the N⁺ polysilicon is adjusted to a value close to that of a corresponding P⁺ polysilicon gate. Hence, the threshold voltage of the p-MOSFET can still be controlled in an acceptable range.

Already a very thin Al_(x)O_(y) layer (monolayer or several monolayers) results in an insignificant increase of the overall gate dielectric effective thickness due to its relatively high dielectric constant of about 7 to 10.

Moreover, there is a good process compatibility with current Si processing compared with using metal gates. The dual work-function concept is without restrictions of the thermal budget due to boron penetration.

Two general approaches are proposed for the formation of the thin high-k dielectric interfacial layer.

The first approach is to deposit the high-k interfacial dielectric layer on top of the gate dielectric layer and to remove the high-k dielectric layer on top of the n-MOSFET regions by selective wet chemistry.

The other approach is to implant appropriate metal irons into p-MOSFET N⁺ polysilicon gate areas after the patterning of the areas. Then, a thermal treatment is performed such that metal irons diffuse to the interface between the N⁺ polysilicon and the gate dielectric where the metal irons will react with gate dielectric (SiO₂, SiO_(x)N_(y) or a different high-k oxide) and form the desired thin interfacial high-k dielectric layer.

According to a preferred embodiment the step of forming a gate structure on the first and second transistor region includes: forming a first dielectric layer in the first and second transistor region; forming the interfacial dielectric layer in the first and second transistor region above the first dielectric layer; masking the interfacial dielectric layer in the second transistor region; removing the interfacial dielectric layer in the first transistor region; and forming the gate layer in the first and second transistor region.

According to another preferred embodiment the step of forming a gate structure on the first and second transistor region includes: forming a first dielectric layer in the first and second transistor region; forming the gate layer in the first and second transistor region; performing an Al ion implantation into the second transistor region; performing a heat treatment for forming the interfacial dielectric layer in second transistor region above the first dielectric layer.

According to another preferred embodiment the semiconductor substrate is provided having first, second and third transistor regions, the first transistor region being a n-MOSFET region, second transistor region being a p-MOSFET region and the third transistor region being a memory array MOSFET, and wherein at least one second dielectric layer is formed simultaneously in all of the first, second and third transistor regions.

According to another preferred embodiment the second dielectric layer is a high-k dielectric layer made of HfO or HfSiO or HfSiON.

According to another preferred embodiment the interfacial dielectric layer is made of a high-k material such as Al_(x)O_(y), Al₂O₃ or HfAl_(x)O_(y) or any material in combination with Al₂O₃ that forms the Al₂O₃ containing interface on the gate layer.

According to another preferred embodiment the gate layer in the first and second transistor regions is made of the same material and electrically connected thereby.

According to another preferred embodiment the gate layer in the first and second transistor regions is made of a different material and electrically connected by a gate contact layer.

According to another preferred embodiment the memory array MOSFET is a RCAT device.

Preferred embodiments of the invention are depicted in the drawings and explained in the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 A,B show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a first embodiment of the present invention;

FIG. 2A,B show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a second embodiment of the present invention;

FIG. 3A-F show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a third embodiment of the present invention; and

FIG. 4A-F show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a fourth embodiment of the present invention.

In the Figures, identical reference signs denote equivalent or functionally equivalent components.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1A,B show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a first embodiment of the present invention.

In FIG. 1, reference sign 1 denotes a silicon semiconductor substrate having a first transistor region T1 as an n-MOSFET region and a second transistor region T2 as a p-MOSFET region. Deposited on top of the substrate 1 there are a base gate dielectric layer 2 of SiO₂ and a thin high-k interfacial dielectric layer 3 of Al_(x)O_(y). Optionally, a thermal treatment can be applied after having deposited the high-k dielectric layer 3.

With reference to FIG. 1B, the layers 2, 3 in the second transistor region T2, i.e. the p-MOSFET region, are protected with a photoresist region 5. Thereafter, the high-k interfacial dielectric layer 3 is selectively removed from the top of the base dielectric layer 2 in the first transistor region T1, i.e. the n-MOSFET region.

Thereafter, the photoresist region 5 is removed from the second transistor region T2 and a (not shown) N⁺ gate polysilicon layer is deposited over the first and second transistor regions T1, T2.

Consequently, a semiconductor structure is obtained, wherein p-MOSFETs in the second transistor region T2 may be obtained with a proper work-function and an acceptable value of the threshold voltage. Simultaneously, n-MOSFET transistors may be obtained in the first transistor region T1 which do not require the additional thin high-k interfacial dielectric layer 3, because an acceptable value of the threshold voltage may be obtained in absence of this high-k dielectric layer 3 by only using the base dielectric layer 2.

FIG. 2A,B show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a second embodiment of the present invention.

In the second embodiment shown in FIG. 2A, 2B, the manufacturing process for obtaining the two transistor regions T1, T2 with different dielectric structures is modified while the finally resulting semiconductor structure is the same as in the first embodiment.

With respect to FIG. 2A, the base dielectric layer 2 of SiO₂ is formed on the first and second transistor regions T1, T2. Thereafter, an N⁺ polysilicon gate layer 4 is deposited and structured on top of the base gate dielectric layer 2.

In the next process step which is illustrated in FIG. 2B, an implantation I of Al ions is performed in the second transistor region T2, only. This may be achieved by appropriately focusing the ion beam or by protecting the first transistor region T1 by means of a (not shown) mask layer.

After a subsequent thermal treatment, Al diffuses into the interface between the base gate dielectric layer in the N⁺ polysilicon gate layer 4 and reacts with the oxide contained in the base gate electric layer 2 thus forming an interfacial Al_(x)O_(y) high-k dielectric layer 3 in the second transistor region T2, only.

Consequently, the same semiconductor structure as in the first embodiment is obtained which has the excellent advantages listed above.

The third and fourth embodiments described below refer to structures having peripheral n-MOSFETs and p-MOSFETs as well as array MOSFETs of RCAT type (recessed channel array transistor).

FIG. 3A-F show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a third embodiment of the present invention.

In FIG. 3A, reference sign T1 denotes a first transistor region for N-MOSFETs, T2 a second transistor region for p-MOSFETs, and T3 a third transistor region for array MOSFETs of the RCAT type.

In order to arrive at the process stage shown in FIG. 3A, STI trenches 7 are formed in the silicon semiconductor substrate 1 and filled within an isolating filling 9 of silicon oxide. Then, well and threshold implants are performed in the first, second and third transistor regions T1, T2, T3. A thin sacrificial oxide layer 10 is formed in the first and second transistor regions T1, T2, whereas a thick oxide layer 10 a is formed on the upper surface 0 of the semiconductor substrate in the third transistor region T3. A step between the oxide layers 10 and 10 a is denoted with reference sign 11.

Moreover, a photoresist layer 15 is deposited and structured on top of the oxide layers 10, 10 a such that an opening 20 is formed in the third transistor region T3. By means of the structured photoresist layer 15 as a mask, the oxide layer 10 a is removed in the opening 20 exposing the underlying third transistor region T3.

With reference to FIG. 3B, the photoresist layer 15 is stripped, and thereafter a trench 21 for an array MOSFET of RCAT type is formed by a suitable edge using the oxide layers 10, 10 a as a mask. Then, the thin sacrificial oxide layer 10 is stripped, in which process step the thick oxide layer 10 a is correspondingly thinned.

As depicted in FIG. 3C, a thick oxide layer 10 d is formed and etched back using a mask for removing it except in the trench 21 for the array MOSFET, the thick oxide layer 10 d forming a first dielectric layer for the array MOSFETs to be formed therein. Then, a thin oxide layer 10 c is formed in the first and second transistor regions T1, T2 and on top of the oxide layer 10 a, the thin oxide layer 10 c forming a first dielectric layer for the n- and p-MOSFETs to be formed therein.

According to FIG. 3D, a second dielectric layer 17 made of a high-k dielectric such as HfO or HfSiO or HfSiON is deposited over the first, second and third transistor regions T1, T2, T3. Thereafter, a third dielectric layer 25 is deposited over the first high-k dielectric layer 17, the third dielectric layer 25 being made of a high-k material such as Al₂O₃ or HfAl_(x)O_(y) or any material in combination with Al₂O₃ that forms an Al₂O₃ rich interface to polysilicon. The third dielectric layer 25 being made of the high-k material is chosen such that it has strong Fermi-level pinning effects on the later N⁺ gate polysilicon. As a consequence, the effective work-function for the N⁺ polysilicon is adjusted to a value close to that of a corresponding P⁺ polysilicon gate. Hence, the threshold voltage of the p-MOSFET can still be controlled in an acceptable range.

Then, a photoresist layer 30 is deposited and structured over the third dielectric layer 25 such that it protects the second transistor region T2, i.e. the p-MOSFET transistor region. Using the structured photoresist layer 30 as a mask, the third dielectric layer 25 is removed in the first and third transistor regions T1, T3, namely by a selective wet edge process.

As shown in FIG. 3E, after the removal of the photoresist layer 30, an N⁺ polysilicon gate layer 35 is deposited and structured such that it only covers the first and second transistor regions T1, T2.

In this process step, the N⁺ polysilicon gate layer 35 is recessed in the trench 21 for the array MOSFET to a level below the surface 0 of the semiconductor substrate 1.

For structuring and recessing the N⁺ polysilicon gate layer 35, a (not shown) photoresist mask may also be used.

With reference to FIG. 3F, another oxide layer 42 is deposited over the first, second and third transistor regions T1, T2, T3 and anisotropically etched resulting in spacers 42 a and 42 b on the N⁺ polysilicon gate layer 35 and in the trench 21 for the array MOSFET in the third transistor region T3, repectively.

Finally, a tungsten layer 40 is deposited and structured in order to form a gate contact on top of the N⁺ polysilicon gate layer 35 in the first, second and third transistor regions T1, T2, T3.

In this example, the N⁺ polysilicon gate layer 35 connects the gates of the first and second transistor regions T1, T2 which is necessary for the electric performance of the corresponding n- and p-MOSFETs.

FIG. 4A-F show schematic cross-sections of a manufacturing method for an integrated semiconductor structure as a fourth embodiment of the present invention.

The process state shown in FIG. 4A is achieved starting from the process state shown in FIG. 3C, namely after forming the thin and thick oxide layers 10 c and 10 d, respectively.

The second dielectric layer 17 made of HfO or HfSiO or HfSiON high-k material is deposited over the first, second and third transistor regions T1, T2, T3. Thereafter, an N⁺ polysilicon gate layer 50 is deposited over the first high-k dielectric layer 17 in the first, second or third transistor regions T1, T2, T3. Then, a photoresist layer 55 is deposited and patterned over the N⁺ polysilicon gate layer 50 such that it only protects the first transistor region T1, which results in the process state shown in FIG. 4A.

In a following process step shown in FIG. 4B, the N⁺ polysilicon gate layer 50 is removed from the second transistor region T2 and recessed in the trench 21 for the array MOSFET in the third transistor region T3. Thereafter, the photoresist layer 55 is removed, and another oxide layer is deposited and anisotropically etched back over the structure such that spacers 42 a′ and 42 b′ are formed on the remaining N⁺ polysilicon gate layer 55 and in the trench 21 for the array MOSFET in the third transistor region T3, respectively.

With reference to FIG. 4C, the second dielectric layer 17 is selectively lithographically removed in the second transistor region T2 while the third transistor region T3 is covered with a (not shown) further photoresist mask such that the second dielectric layer 17 is left in the first and third transistor region T3, only, as shown in FIG. 4C. In this process step, also oxide layer 10 c is removed and thereafter renewed in the second transistor region T2.

Then, with reference to FIG. 4D, a sacrificial thermal oxide layer 10 e is formed on the remaining N⁺ polysilicon gate layer 55 in the first and third transistor regions T1, T3. Thereafter, a third dielectric layer 25′ is deposited over the first, second or third transistor regions T1, T2, T3, the third dielectric layer 25′ being made of a high-k material such as Al₂O₃ or HfAl_(x)O_(y) or any material in combination with Al₂O₃ that forms an Al₂O₃ rich interface to polysilicon. The third dielectric layer 25 being made of the high-k material is chosen such that it has strong Fermi-level pinning effects on the later N⁺ gate polysilicon. As a consequence, the effective work-function for the N⁺ polysilicon is adjusted to a value close to that of a corresponding P⁺ polysilicon gate. Hence, the threshold voltage of the p-MOSFET can still be controlled in an acceptable range.

Finally, a N⁺ polysilicon gate layer 60 is formed on the second high-k dielectric layer 25′ resulting in the structure shown in FIG. 4D.

With reference to FIG. 4E, a further photomask 61 is formed and structured such that it only protects the second transistor region T2. Using this photomask 61, the N⁺ polysilicon gate layer 60 is removed except for the second transistor region T2. This removal is performed by an etching process which stops on the third dielectric layer 25′. In a subsequent anisotropic etch step, the third dielectric layer is removed from the plane surfaces of the exposed plane surfaces of the first, second and third transistor regions T1, T2, T3 such that the third dielectric layer 25′ only remains at the vertical surfaces and below the remaining N⁺ polysilicon gate layer as may be obtained from FIG. 4E. Thereafter, the photoresist mask 61 is stripped from the top of the remaining N⁺ polysilicon gate layer 60.

Finally, the oxide layer 10e is removed and a tungsten layer 70 is deposited over the entire structure in order to provide gate contacts on the N⁺ polysilicon gate layers 55 and 60 in the first, second and third transistor regions T1, T2, T3.

In this example, the tungsten layer 70 connects the gates of the first and second transistor regions T1, T2 which is necessary for the electric performance of the corresponding n- and p-MOSFETs.

Although the present invention has been described with respect to two preferred embodiments, it is not limited thereto, but can be modified in various manners which are obvious for the person skilled in the art.

Particularly, the selection of the materials is only an example and can be varied variously.

Especially, the gate structure in the second transistor region may also be formed by a depositing polysilicon on Al₂O.₃ containing interface, and thereafter performing a full silicidation which leaves an interface polysilicon layer.

Alternatively, the gate structure in the second transistor region may also be formed by a depositing silane on Al₂O.₃ containing interface to form a polysilicon interface, and thereafter depositing a metal gate layer on top of the interface, i.e. tungsten or TiN. 

1. A method of manufacturing an integrated semiconductor structure, the method comprising: forming a first transistor at a surface of a semiconductor body, the first transistor comprising a gate overlying a first gate dielectric, the first gate dielectric not including aluminum oxide; and forming a second transistor at the surface of the semiconductor body, the second transistor being a different conductivity type than the first transistor, the second transistor comprising a polysilicon gate overlying a second gate dielectric, the second gate dielectric comprising an aluminum oxide layer between an underlying dielectric layer and the polysilicon gate.
 2. The method of claim 1, wherein the first transistor comprises an n-channel transistor and the second transistor comprises a p-channel transistor.
 3. The method of claim 2, wherein the first gate dielectric comprises silicon oxide and wherein the underlying dielectric layer of the second gate dielectric comprises silicon oxide.
 4. The method of claim. 3, wherein the first gate dielectric layer comprises SiO₂ and wherein tie second gate dielectric layer comprises Al₂O₃ overlying SiO₂.
 5. (canceled)
 6. The method of claim 2, wherein the aluminum oxide layer comprises an Al₂O₃ interfacial dielectric layer located adjacent to the n-doped polysilicon gate that causes a Fermi-pinning effect. 7-9. (canceled)
 10. The method of claim 1, wherein forming the second transistor comprises depositing polysilicon and then performing a full silicidation that leaves an interface polysilicon layer.
 11. The method of claim 2, wherein forming the p-channel transistor comprises depositing silane on the aluminum oxide layer to form a polysilicon interface.
 12. The method of claim 11, further comprising depositing a metal gate layer over the polysilicon interface.
 13. The method of claim 12, wherein the metal gate layer comprises tungsten and/or TiN.
 14. The method of claim 2, wherein forming the first transistor and forming the second transistor comprise: forming a first dielectric layer over the semiconductor body; forming a second dielectric layer over the first dielectric layer; and removing the second dielectric layer from location where the n-channel transistor will be formed. 15-16. (canceled)
 17. The method of claim 1, wherein forming the first transistor and forming the second transistor comprise: forming a first dielectric layer over the semiconductor body; and implanting Al ions into a portion of the first dielectric layer to form the aluminum oxide over the underlying dielectric layer.
 18. The method of claim 1, wherein the semiconductor body includes a first region, a second region and a third region, the first transistor being formed in the first region, the second transistor being formed in the second region and a memory array memory array transistor being formed in the third region.
 19. The method of claim 18, wherein at least one dielectric layer is formed simultaneously in all of said first, second and third regions.
 20. The method of claim 19, wherein at least one high-k dielectric layer is formed simultaneously in all of said first, second and third regions.
 21. The method of claim 20, wherein the high-k dielectric layer comprises HfO or HfSiO or HFSiON.
 22. The method of claim 18, wherein the memory array transistor comprises a recessed channel array transistor.
 23. (canceled)
 24. The method of claim 1, wherein the aluminum oxide layer is made of Al_(x)O_(y) or Al₂O₃ or HfAl_(x)O_(y) or any material in combination with Al₂O₃ that forms the aluminum oxide layer.
 25. An integrated semiconductor structure, comprising: an n-channel transistor at a surface of a semiconductor body, the n-channel transistor comprising a polysilicon gate overlying a first gate dielectric; and a p-channel transistor at the surface of the semiconductor body, the p-channel transistor comprising an n-doped polysilicon gate overlying a second gate dielectric, the second gate dielectric comprising an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.
 26. The integrated semiconductor structure according to claim 25, wherein the aluminum oxide is in physical contact with both the underlying dielecric layer and the n-doped polysilicon gate.
 27. The integrated semiconductor structure according to claim 25, wherein aluminum oxide layer comprises Al₂O₃.
 28. The integrated semiconductor structure according to claim 25, wherein the aluminum oxide layer is thinner than both the underlying dielectric layer and the n-doped polysilicon gate.
 29. The integrated semiconductor structure according to claim 25, wherein the underlying dielectric layer comprises an oxide layer.
 30. The integrated semiconductor structure according to claim 29, wherein the underlying dielectric layer comprises a silicon oxide layer.
 31. A semiconductor device, comprising: a substrate; a gate stack comprising an oxide dielectric and an electrode overlying the substrate; and a high-k dielectric layer containing aluminum oxide disposed between the oxide dielectric layer and the electrode.
 32. The semiconductor device according to claim 31, wherein the high-k dielectric layer containing aluminum oxide is formed in physical contact with the substrate, and wherein the electrode is formed in physical contact with the high-k dielectric layer containing aluminum oxide.
 33. The semiconductor device according to claim 32, wherein the high-k dielectric layer contains Al₂O₃.
 34. The semiconductor device according to claim 32, wherein the electrode comprises polysilicon.
 35. The semiconductor device according to claim 31, wherein the high-k dielectric layer is thinner than the dielectric layer and the electrode.
 36. A method of fabricating a semiconductor device, the method comprising: providing a substrate with a first region and a second region; forming a first dielectric layer over the substrate; forming a second dielectric layer on the first dielectric layer, the second dielectric layer comprising an aluminum compound; forming a mask layer over the first region and the second region; removing the mask layer from over the first region thereby exposing the second dielectric over the first region; removing the exposed second dielectric layer from over the first region; removing the mask from over the second region; and depositing a conductive material over the first and the second region.
 37. The method according to claim 36, wherein the second dielectric layer is thinner than the first dielectric layer and the conductive material.
 38. The method according to claim 36, wherein aluminum compound comprises aluminum oxide.
 39. The method according to claim 38, wherein aluminum compound comprises Al₂O₃.
 40. The method according to claim 36, further comprising heating the substrate after depositing the second dielectric layer.
 41. The method according to claim 36, wherein the conductive material comprises N⁺ doped polysilicon.
 42. A method of fabricating a semiconductor devices the method comprising: providing a substrate with a first region and a second region; forming a dielectric layer over the substrate; forming a conductive material on the dielectric layer; doping the dielectric layer over the second-region with Al ions; and subjecting the device to a thermal treatment after the doping.
 43. The method according to claim 42, wherein doping the dielectric layer comprises doping with an ion beam,
 44. The method according to claim 42, wherein doping the dielectric layer comprises: providing a mask layer over the conductive material of the first region; doping the device with Al ions; and removing the mask layer.
 45. The method according to claim 42, wherein subjecting the device to a thermal treatment forms an Al₂O₃ layer.
 46. The method according to claim 42, wherein the conductive material comprises N+ doped polysilicon.
 47. The method of claim 1, wherein the polysilicon gate comprises an n-doped polysilicon gate. 